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ISL8510
Figure 31 shows an asymptotic plot of the DC/DC
converter ’s gain vs frequency. The actual Modulator Gain
has a high gain peak due to the high Q factor of the output
filter and is not shown in Figure 31. Using the guidelines
from “Modulator Break Frequency Equations” on page 18
should give a Compensation Gain similar to the curve
plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at f P2
with the capabilities of the error amplifier. The Closed Loop
Gain is constructed on the graph of Figure 31 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain.
The compensation gain uses external impedance networks
Z FB and Z IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin.
load current. During turn-off, current stops flowing in the
MOSFET and is picked up by the lower MOSFET. Any
parasitic inductance in the switched current path generates a
large voltage spike during the switching interval. Careful
component selection, tight layout of the critical components,
and short, wide traces minimizes the magnitude of voltage
spikes.
There are two sets of critical components in the ISL8510
switching converter. The switching components are the most
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next are
the small signal components, which connect to sensitive
nodes or supply critical bypass current and signal coupling.
A multi-layer printed circuit board is recommended.
Figure 32 shows the connections of the critical components
in the converter. Note that capacitors C IN and C OUT could
each represent numerous physical capacitors. Dedicate one
solid layer (usually a middle layer of the PC board) for a
ground plane and make all critical component ground
connections with vias to this layer. Dedicate another solid
100
f Z1 f Z2
f P1
f P2
layer as a power plane and break this plane into smaller
islands of common voltage levels. Keep the metal runs from
80
the PHASE terminals to the output inductor short. The power
60
40
20LOG
OPEN LOOP
ERROR AMP GAIN
plane should support the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
20
(R 2 /R 1 )
20LOG
circuit layers for small signal wiring. The wiring traces from
0
-20
MODULATOR
GAIN
(V IN / Δ V OSC )
COMPENSATION
GAIN
the GATE pins to the MOSFET gates should be kept short
and wide enough to easily handle the 1A of drive current.
-40
-60
10
100
1k
f LC
10k
f ESR
100k
1M
CLOSED LOOP
GAIN
10M
5V
PVCC
VIN
V IN
FREQUENCY (Hz)
C BP1
ISL8510
C IN
FIGURE 31. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
A more detailed explanation of voltage mode control of a
buck regulator can be found in Tech Brief TB417, entitled
“Designing Stable Compensation Networks for Single Phase
R BP
C BP2
VCC
PHASE
PGND
D
L
C OUT1
V OUT1
Voltage Mode Buck Regulators.”
http://www.intersil.com/data/tb/tb417.pdf
Layout Considerations
Layout is very important in high frequency switching
converter design. With power devices switching efficiently at
COMP
FB
C 2
R 2
R 4
C 1
R 1
C 3
R 3
500kHz, the resulting current transitions from one device to
another cause voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device overvoltage stress. Careful component
layout and printed circuit board design minimizes these
voltage spikes.
As an example, consider the turn-off transition of the control
MOSFET. Prior to turn-off, the MOSFET is carrying the full
19
GND PAD
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 32. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
FN6516.2
December 15, 2008
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